Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• Candidates will typically have 3 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.

• Experience with CMOS technology and device physics.

• Experience in reliability modeling, data analytics, and statistics.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Data Analytics experience and ability to identify commonalities and abnormalities.

• Knowledge of semiconductor device physics, failure mechanisms, and accelerated test methodologies.

• Knowledge of JEDEC and other industry-standard reliability specifications. Working knowledge of Design-for-Reliability guidelines and implementation techniques.

• Excellent communication and collaboration skills.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Develop and implement physics-based statistical Quality and Reliability models (ELF, TDDB, NBTI, HCI, Time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

• Collaborate with cross-functional teams to develop product Design-for-Reliability resilience based on product mission profile, technology node guidelines, modeling and analysis findings (e.g., SER, EMIR, PERC, HVDRC, Aging, etc. ).

• Extract, manipulate, and analyze large volumes of data from Silicon and Package qualification programs (e.g., HTOL, ELFR, ESD, LU, UHAST, TCT, etc. ), High Volume MFG, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield and quality and reliability improvement.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.